1. Field of the Invention
The present invention relates to a clock extracting device for extracting a clock synchronous in phase with information signals read from a disklike information recording medium (hereinafter, referred to as a “disc”), which is employed in a disc reproducing apparatus for recording the information signals at the extracted clock.
2. Description of the Prior Art
A constant linear velocity (CLV) recording method is known as one of the methods for recording information signals on a disc. In order to read from the disc the information signals subjected to CLV recording, it is necessary to provide a clock extracting circuit for extracting a clock synchronous in phase with the information signals.
A conventional clock extracting circuit is described with reference to FIG. 11 showing a first example of a clock extracting device of a conventional optical disc reproducing apparatus. In FIG. 11, information signals fetched from an optical disc 1 by an optical pickup 2 are inputted to one input terminal of a phase comparator 3 and one input terminal of a frequency comparator 8. Outputs of the phase comparator 3 and the frequency comparator 8 control a charge pump 4 and an output of the charge pump 4 is not only applied to a series circuit of a resistor R1 and a capacitor C1 but inputted to a voltage control oscillator 5. A portion of an output PCK of the voltage control oscillator 5 is applied to the other input terminal of the phase comparator 3 and the other input terminal of the frequency comparator 8.
The frequency comparator 8 compares a clock frequency to be extracted from the information signals and a frequency of the output PCK of the voltage control oscillator 5 so as to yield a frequency comparison output. The charge pump 4 is operated in accordance with the frequency comparison output of the frequency comparator 8 and the voltage control oscillator 5 is operated under control of a control voltage produced by the series circuit of the resistor R1 and the capacitor C1 such that the frequency of the output PCK of the voltage control oscillator 5 is made coincident with the clock frequency to be extracted from the information signals. When the frequency of the output PCK of the voltage control oscillator 5 has been made coincident with the clock frequency to be extracted from the information signals, output of the frequency comparator 8 is stopped and the phase comparator 3 is operated so as to make a phase of the information signals coincident with a phase of the output PCK of the voltage control oscillator 5.
Operation of the phase comparator 3 is described hereinafter on the supposition that “θREF” denotes the phase of the information signals, “θOSC” denotes the phase of the output PCK of the voltage control oscillator 5, “Kφ” (A/rad) denotes a phase-current conversion gain of a combination of the phase comparator 3 and the charge pump 4, “KV” (Hz/V) denotes a voltage-frequency conversion gain of the voltage control oscillator 5, “I” denotes an output current flowing through the charge pump 4 under control of the phase comparator 3, “F” denotes a transfer function of the series circuit of the resistor R1 and the capacitor C1, “j” and “ω” denote an imaginary unit and an angular frequency in Fourier transform, respectively and “s” satisfies a relation of (jω=s).
At this time, the phase comparator 3 compares the phase of the information signals read from the optical disc 1 by the optical pickup 2 and the phase of the output PCK of the voltage control oscillator 5 and outputs the current I corresponding to the phase difference as follows.(θREF−θOSC)Kφ=I  (1)
Then, the output of the charge pump 4 is converted into a voltage V as follows by the series circuit of the resistor R1 and the capacitor C1, whose one end is connected to the output of the charge pump 4 and the other end of which is grounded or is connected to a reference voltage.I×F=V  (2)
Supposing that the resistor R1 has a resistance R and the capacitor C1 has a capacity C, the transfer function F of the series circuit of the resistor R1 and the capacitor C1 is expressed as follows.F=R+1/(s×C)  (3)
Meanwhile, the frequency of the output PCK of the voltage control oscillator 5 is changed by using an output of the series circuit as the control voltage such that the following relation is established.s×θOSC=KV×V  (4)
By substituting I of the equation (2) and V of the equation (4) for the equation (1), the following equation is obtained.(θREF−θOSC)Kφ=s×θOSC/(KV×F)
Then, this equation is changed as follows.θOSC/θREF=G/(1+G)  (5)
In the equation (5), “G” satisfies the following relation.G=Kφ×KV×F/s  (6)
The equation (5) represents open loop characteristics of this conventional clock extracting circuit. It will be understood from the equation (6) that a loop gain of this conventional clock extracting circuit is proportional to a product of the gain of the phase comparator 3 and the gain of the voltage control oscillator 5.
As a read rate of the information signals is raised further, fluctuations of jitter become larger. Thus, a necessary loop gain of the clock extracting circuit becomes large in accordance with a magnitude of the error. For example, in the CLV recording method, the number of revolutions at an inner periphery of the optical disc 1 is different from that at an outer periphery of the optical disc 1 in order to secure a constant linear velocity. Therefore, when the optical pickup 2 is displaced through a large distance from the inner periphery to the outer periphery of the optical disc 1, a linear velocity at the outer periphery of the optical disc 1 becomes higher than that at the inner periphery of the optical disc 1, so that the read rate is also raised accordingly and thus, the necessary loop gain of the clock extracting circuit also changes greatly. This phenomenon becomes more conspicuous as the read rate of the information signals rises further. Therefore, the necessary loop gain of the clock extracting circuit changes according to the read rate of the information signals. Accordingly, in order to ensure stable reproduction of the information signals from the inner periphery to the outer periphery of the optical disc 1, it is necessary to change the loop gain of the clock extracting circuit in accordance with the read rate of the information signals.
A method of changing over a loop gain of a known clock extracting circuit is described with reference to FIG. 12 showing a second example of the clock extracting device of the known optical disc reproducing apparatus. FIG. 12 is different from FIG. 11 in that an output of the voltage control oscillator 5 is connected to one input of a changeover switch 33 and is also connected to the other input of the changeover switch 33 via a frequency divider 31 for performing frequency division of the output of the voltage control oscillator 5 to a half and a speed setter 32 is provided for effecting changeover of the changeover switch 33.
In accordance with an output of the speed setter 32, the changeover switch 33 is changed over to one of a state in which the changeover switch 33 is directly connected to the voltage control oscillator 5 and a state in which the changeover switch 33 is connected to the voltage control oscillator 5 through the frequency divider 31. Namely, when the output of the speed setter 32 is of 1-time speed, the changeover switch 33 is connected to the frequency divider 31. On the other hand, when the output of the speed setter 32 is of 2-time speed, the changeover switch 33 is directly connected to the output of the voltage control oscillator 5.
As described above, conventionally, the changeover switch 33 is changed over in accordance with speed set by the speed setter 32 so as to change a voltage-frequency conversion gain of the voltage control oscillator 5 such that changeover of the loop gain of the clock extracting circuit is effected.
However, even if actual read rate of the information signals changes greatly as in the case where the optical pickup 2 is displaced through a large distance from the inner periphery to the outer periphery of the optical disc 1, the loop gain of the prior art clock extracting circuit is determined by the preset speed and thus, operation of the prior art clock extracting circuit becomes unstable when the set speed is not coincident with the actual read rate. For example, in case the actual read rate of the information signals is lower than the set speed, the loop gain rises due to frequency pulling upon operation of the frequency comparator 8, so that in the worst case, oscillation leads to a state in which the clock frequency to be extracted from the information signals does not become coincident with the frequency of the output of the voltage control oscillator 5. Meanwhile, even when the clock frequency to be extracted from the information signals is coincident with the frequency of the output of the voltage control oscillator 5, rise of the loop gain due to phase lock upon operation of the phase comparator 3 may lead, in the worst case, to a state in which it is impossible to extract the clock by oscillation.
Thus, in the clock extracting device of the prior art disc reproducing apparatus, such a disadvantage is incurred that although it is necessary to change the loop gain of the clock extracting circuit in accordance with the continuously changing read rate of the information signals, the loop gain of the clock extracting circuit is changed only when the read rate of the information signals has been set.